The present invention generally relates to a driving apparatus and a driving method for a liquid crystal display having a plurality of row electrodes and column electrodes. More particularly, the present invention relates to a liquid crystal display or other matrix-type display apparatus suited to using a multiple line selection drive method, and relates specifically to an improvement of primarily the matrix-type display element module, controller, and signal electrode driver circuit.
In a simple matrix-type liquid crystal display commonly used for flat panel display devices, the display data from a microprocessor unit (MPU) is typically transferred to the LCD module (the liquid crystal display panel (LCD panel)), the scan electrode drive circuit (Y driver), and the signal electrode drive circuit (X driver) using one of two basic methods: using a matrix-type liquid crystal display element module controller (simply xe2x80x9cmodule controllerxe2x80x9d below), or using an X driver embedded in RAM.
The module controller method is described first. As with a CRT display apparatus, the module controller connected to the system bus reads the display data from video RAM (VRAM), and sends the data to the LCD module at a high frequency to refresh the display.
In the latter method, a dual port frame memory (built-in RAM) is provided in the X driver. This frame memory is directly accessed by the MPU via the data bus, control bus, or address bus irrespective of the LCD timing to generate the required control signal in the X driver by changing the display data in the frame memory. One scan line equivalent of display data is simultaneously read from the built-in frame memory to refresh the display.
With the module controller method above, VRAM data access and transfer coordinated with the LCD timing must be executed each time the display screen is changed, and it is therefore necessary for the VRAM, module controller, and LCD driver to constantly operate at a high frequency. In addition, the display refresh operation involves operation of the VRAM, module controller, and LCD driver. Operation of an LSI device at a high frequency clock results in through-current flowing to the plural CMOS devices used as circuit elements, increasing the total current consumption. Total current consumption also increases in direct proportion to the size of the LCD panel. In addition, while the VRAM is accessed by both the MPU and the module controller, a high speed clock must be used so that MPU access during the display refresh operation does not collide with module controller access, thus limiting the use of a low frequency operating module controller and limiting the processing ability of the MPU.
Operation at a low frequency clock is possible in the latter method above because there is no relationship between display data transfer and LCD timing. This method thus requires 10-100 times less power than the module controller method. When using a large liquid crystal panel, however, the number of X drivers must be increased.
The number of X driver output terminals is generally a multiple of ten (e.g., 160 pins) and not a power of two (e.g., 2n), however, because each RAM device built into the X drivers has an independent address area. When the internal memory of plural X drivers is addressed by the MPU, the MPU finds apparent gaps in the total memory area, and it is usually difficult to maintain a continuous sequence of addresses. As a result, the address coordination process of the MPU must be executed at high speed when the entire display area is changed at one time as during scrolling or panning operations, significantly increasing the processing load on the MPU.
It is, of course, possible to design the X driver ICs to have an exponent-of-two number of output pins, but this would seriously impair system interchangeability because compatibility with the number of electrodes in existing LCD panels would be lost. In addition, use of plural X drivers necessarily increases the number of chip selection buses, and sufficient space for this plural number of X drivers to be installed around the LCD panel must be provided. This reduces the display area ratio of the display panel, and inhibits the potential size reduction of the LCD module. The latter method above is therefore unsuited to large scale liquid crystal panels.
Matrix liquid crystal displays such as, twisted nematic (TN) and super twisted nematic (STN), are known in the art. Reference is made to FIGS. 21A-21E and FIG. 22 in which a conventional matrix liquid crystal display is provided. A liquid crystal panel generally indicated as 1 is composed of a liquid crystal layer 5, a first substrate 2 and a second substrate 3 for sandwiching the liquid crystal layer 5 therebetween. A group of column electrodes Y1-Ym are oriented on substrate 2 in the vertical direction and a plurality of row electrodes X1-Xn are formed on substrate 3 in substantially the horizontal direction to form a matrix. Each intersection of column electrodes Y1-Ym and row electrodes X1-Xn forms a display element or pixel 7. Display pixels 7 having the open circle indicate an ON state and those pixels having a blank indicate an OFF state.
A conventional multiplex driving based on the amplitude selective addressing scheme is known to one of ordinary skill in the art as one method of driving the liquid crystal cells mentioned above. In such a method, a selected voltage or non-selected voltage is sequentially applied to each of row electrodes X1-Xn individually. That is, a selection voltage is applied to only one row electrode at a time. In the conventional driving method, the time period required to apply the successive selected or non-selected voltage to all the row electrodes X1-Xn is as one frame period, indicated in FIGS. 21A-21E as time period F. Typically the frame period is approximate {fraction (1/60)} th of a second or 16.66 milliseconds.
Simultaneously to the successive application of the selected voltage or the non-selected voltage to each of the row electrodes X1-Xn, a data signal representing an ON or OFF voltage is applied to column electrodes Y1-Ym. Accordingly to turn on a pixel 7, the area in which the row electrode intersects the column electrode, to the ON state, an ON voltage is applied to a desired column electrode when the row electrode is selected.
Referring specifically to FIGS. 21A-21E, a conventional multiplex drive method of a simple matrix type liquid crystal and more specifically the amplitude selective addressing scheme is shown therein. FIGS. 21A-21C show the row selection voltage waveforms that is applied in sequence to row electrodes X1, X2 . . . Xn, respectively. More particularly, in time period t1, a voltage pulse having a magnitude of V1 is applied to row electrode X1, and a voltage of zero is applied to electrodes X2-Xn; in time period t2, a voltage pulse having a magnitude of V1 is applied to row electrode X2 and a voltage of zero is applied to electrodes X1 and X3-Xn; and in time period tn, V1 is applied to row electrode Xn and a voltage of zero is to electrodes X1-Xn-1. In other words, a voltage pulse having a magnitude of V1 is applied to only one row electrode Xi in time ti. Typically, ti is approximately 69 xcexc seconds and V1 is approximately 25 volts. As will be apparent to one who has read this description, all of the row electrodes are sequentially selected in time periods t1-tn or one frame period F.
FIG. 21D shows the waveform applied to column electrode Y1, and FIG. 21E shows the synthesized voltage waveform applied to the pixel 71,1 formed at the intersection of the column electrode Y1 and the row electrode X1. As shown therein, during time period t1, a voltage pulse having a magnitude of V1 is applied to row X1 and a voltage pulse of xe2x88x92V2 is applied to column electrode Y1. Typically, V2 is approximately 1.6 volts. The resultant voltage at pixel 71,1 is xe2x88x92(V1-V2). This synthesized voltage is sufficient to turn pixel 71,1 to its ON state.
One known problem with this method is that in order to select and drive the one line of the row electrodes, a relatively high voltage is required to provide good display characteristics, such as, contrast and low distortion. These conventional displays, requiring such a high voltage, also consume relatively more energy. When such displays are used in portable devices, they are supplied with electrical energy by, for example, batteries. As a result of the higher energy consumption, the portable devices have relatively shorter times of operation before the batteries require replacement and/or recharging.
Various attempts have been made to overcome this problem. For example, it has been suggested in xe2x80x9cA Generalized Addressing Technique for RMS Responding Matrix LCDs,xe2x80x9d 1988 International Display Research Conference, pp. 80-85. to simultaneously applying a row selection voltage to more than one row electrode.
As shown in FIGS. 23A-23D, a conventional method for driving a liquid crystal display by simultaneously selecting a group of more than one row electrode is shown. As shown therein, the n row electrodes are divided in j groups of row electrodes, each group comprising, for example, two row electrodes. In this example, row electrodes X1, X2; X3, X4; and Xnxe2x88x921, Xn, each form a group of row electrodes.
Referring again to FIG. 23A, that figure illustrates row selection voltage waveforms applied simultaneously to both row electrodes X1 and X2 in time periods t1 and t2 and a voltage of zero is applied to row electrodes X1 and X2 in the remaining time periods of frame period F. Similarly, FIG. 23B indicates the row selection voltage waveforms applied to row electrodes X3 and X4, during time periods t3 and t4 and a voltage of zero is applied to row electrodes X3 and X4 in the other time periods of frame period F. FIG. 23C illustrates the voltage waveform applied to column electrode Y1, and FIG. 23D indicates the synthesized voltage waveform applied to the pixel 71,1. Generally, t1, t2, . . . tn=69 xcexc seconds, V1 is approximately 17.6 volts and V2 is approximately 2.3 volts.
As shown in the example of FIGS. 23A-23D, every two row electrodes are selected in sequence. In the first selection sequence, two row electrodes, X1 and X2, are selected and row selection voltage waveforms such as that shown in FIG. 23A are applied to each row electrode. At the same time, the designated column voltage, which is described below, is applied to each column electrode, Y1 to Ym. Next, row electrodes X3 and X4 are simultaneously selected with substantially the same type of waveform voltages as that described above. At the same time, the column voltages Y1 to Ym are applied to each column electrode. One frame period represents the selection of all row electrodes, X1 to Xn. In other words, a complete image is displayed during one frame.
As will be explained hereinbelow, when h row electrodes are simultaneously selected, the voltage waveforms that apply the row electrodes described above use 2h row-select patterns. In the example illustrated in FIGS. 23A-23D, the number of row electrodes simultaneously selected is two, thus the number of row select patterns is 22 or4.
Moreover, the column voltages applied to each column electrode Y1 to Ym provide the same number of pulse patterns as that of the row select pulse patterns. That is, there are 2h pulse patterns. These pulse patterns are determined by comparing the states of pixels on the simultaneously selected row electrodes i.e., whether the pixels are ON or OFF, with the polarities of the voltage pulses applied to row electrode.
In this example, as shown in the previously described FIGS. 23A-23D when row electrodes X1 and X2 are selected and row voltages such as those in FIG. 23A and FIG. 24A are applied thereto and when the pixels on row electrodes X1 and X2 are ON and OFF, respectively, the voltage waveform applied the column electrode is voltage waveform Ya shown in FIG. 24B. When the pixels are OFF and ON, respectively, the column voltage waveform Yb is applied to the column electrode. In another example, when the pixels are both ON, a voltage waveform Yc is applied to the column electrode. Finally, when both pixels are OFF, the a column voltage waveform Yd is applied to the column electrode.
The above-mentioned column voltage waveforms Ya-Yd are determined as follows. At first, each pixel simultaneously selected is defined to have a first value of 1 when the voltage applied by the row electrode to the corresponding selected pixel is positive or a first value of xe2x88x921 when the row electrode is negative. Each of the selected pixels is defined to have a second value of xe2x88x921 when the display state is ON or a second value of 1 when display state is OFF. The first value is compared to the second value bit-by-bit, the difference between the number of matches, i.e., when the first value equals the second value, and the number of mismatches, i.e., when the first value does not equal the second value, is calculated. When the difference between the number of matches and mismatches for the simultaneously selected rows is two, V2 is applied; when 0, V0 is applied; and when xe2x88x922, xe2x88x92V2 is applied.
For example, when the pulse waveforms shown in FIG. 23A are applied to row electrodes X1 and X2, a column voltage having the waveform of Ya is applied. This column voltage is determined as follows. The pixels formed at the intersections of column electrode Y1 and rows electrodes X1 and X2 are in the ON and OFF states, respectively. For the purposes of this discussion, these pixels will be referred to as the first and second pixels, respectively. In other words, the first pixel has a second value of xe2x88x921 and the second pixel has a second value of 1. During the period ta, the first pixel has a first value of xe2x88x921 and the second pixel has a first value of xe2x88x921, since the row voltages X1 and X2 are both xe2x88x92V1. Referring to the first pixel, since the first value is xe2x88x921 and the second value is xe2x88x921, there is a match. With regard to the second pixel, the first value is xe2x88x921 and the second value is 1, thereby forming a mismatch. The difference between the number of mismatches and matches is 1xe2x88x921 or zero. Therefore, a voltage of 0 (zero) is applied to the column electrode in time ta. Next, concerning the pulse waveforms of the time interval tb, the applied voltage of row electrode X1 is positive and the applied voltage of row electrode pulse X2 is negative. Using a similar analysis as described above, the number of matches is zero and the number of mismatches is 2. Thus, xe2x88x92V2 volts will be applied to the second half of time interval t1.
As should now be apparent, the first values in time interval tc in FIG. 23A are xe2x88x921 and 1 because the applied voltage of row electrode X1 is negative and the applied voltage of row electrode X2 is positive. When these are compared with the second values of the first and second pixels of xe2x88x921 and 1, the number of matches is two and the number of mismatches is zero. The difference between the number of matches and the number of mismatches is 2. Thus, the column voltage of V2 volts will be applied in time interval tc.
In time interval td, the applied voltage of row electrodes X1 and X2 are both positive. Thus, the first values are 1 and 1. When compared to the pixel states of xe2x88x921 and 1, the number of matches is 1 and the number of mismatches is 1, thus the difference between the number of matches and the number of mismatches is zero. Accordingly, zero volts will be applied to Ya for the time interval td.
A summary of this analysis for time periods ta, tb, tc and td, is shown in Table A below:
As is readily apparent, the column voltage Ya corresponds to the column voltage pattern and is applied to the column to place the first pixel in its ON state and the second pixel in its OFF state.
As for the other column voltage waveforms, Yb to Yd, the voltages are selected under the same criteria as described above and are summarized in Tables B, C and D hereinbelow:
In the examples above, the first value is 1 when the row-select voltage has a positive polarity or the first value when the row-select voltage has a negative polarity. Additionally, the second value is xe2x88x921 when the display state of the pixel is ON, or 1 when the display state is OFF. The column voltage waveforms were selected by means of the difference between the number of matches and the number of mismatches. As will be appreciated by one of ordinary skill in the art, the sign conventions may be inverted. Moreover, it also is possible to set the column voltage waveforms with only the number of matches or the number of mismatches, without having to calculate the difference between the number of matches and the number of mismatches as explained below.
FIGS. 25A-25E illustrate another example of the prior art in which a plurality of row electrodes are divided into groups of row electrodes. The groups of row electrodes are selected in sequence and the row electrodes within each group are simultaneously selected. In this example, each group comprises three row electrodes that are simultaneously selected in order to generate a display pattern, as shown in FIG. 26.
In other words, initially three row electrodes, X1, X2 and X3, are selected and row selection voltages such as those shown in FIG. 25A are applied to these row electrodes, X1, X2 and X3, respectively. At the same time, the designated column voltages, to be discussed later, are applied to each column electrode Y1 to Ym. Next, row electrodes X4, X5 and X6, shown in FIG. 26, are selected and row selection voltages such as that in FIG. 25B are applied to these electrodes in the same manner as described above. At the same time, column voltages are applied to each column electrode, Y1 to Ym. As with the previous example, one frame period F is defined as the selection of all of the row electrodes, X1 to Xn. One image is completely displayed in one frame period, and plural images can be display by repeating this cycle continuously.
When each row voltage waveform described above has h as the number of row electrodes that are simultaneously selected, as in previous example, the number of 2h row-select pattern are used. In this example, the number of 23 or 8 patterns are used.
Moreover, as in the previous example, the column voltages applied to each column electrode, Y1 to Ym, are the same as the number of row-select patterns. Also, the voltage level of each pulse is such that the voltage that corresponds to the numbers of the ON state and the OFF state of the selected row electrodes is applied. In other words, the column voltage level is determined by comparing the row-select pattern and display pattern. Thus, for example, when the row voltage waveforms applied to row electrodes X1, X2 and X3, which are selected simultaneously in this example, have a positive pulse, they are ON, and when they have a negative pulse, they are OFF. The ON and the OFF of the display data are compared at each pulse and the column voltage waveforms are set according to the number of mismatches.
In other words, in the example of FIGS. 25A-25D, when the number of mismatches is zero, xe2x88x92V3 volts are applied; when it is 1, xe2x88x92V2 volts are applied; when it is 2, V2 volts are applied; and when it is 3, V3 volts are applied. The voltage ratios for V2 and V3 above are preferably such that V2: V3=1:3
In specific terms, in the case of the voltage waveforms applied to row electrodes X1, X2 and X3 in FIG. 25A, those waveforms are ON when the V1 volts are applied and OFF when the xe2x88x92V1 volts are applied. Referring to FIG. 26, the pixel is indicated as ON when there is a closed circle and OFF when there is a open circle. As shown in FIG. 26, the display states of the pixels that cross with column electrode Y1 and row electrodes X1, X2 and X3 are ON, ON and OFF, respectively. In contrast to this, the initial pulse pattern of the voltage applied to each row electrode, X1 , X2 and X3, is OFF, OFF and OFF, respectively. Comparing both in sequence, the number of mismatches is 2. Therefore, V2 volts are applied to the initial pulse pattern of the voltage applied to each row electrode Y1, as shown in FIG. 25C. Using a similar analysis, the second pulse pattern of the voltage that is applied to each row electrode, X1, X2 and X3, is OFF, OFF and ON, respectively. When compared in sequence the voltage pattern with the ON, ON and OFF sequence of the aforesaid pixel display pattern, all are mismatching. Since the number of mismatches is 3, voltage V3 is applied to the second pulse of column electrode Y1. As will be understood by one of ordinary skill in the art, by applying the above described analysis to the third and fourth time intervals, column voltages xe2x88x92V2 and xe2x88x92V2 are applied therein. Thus, a column voltage of xe2x88x92V3, V2, xe2x88x92V2 and xe2x88x92V2 is applied to provide the pixel states as shown in FIG. 26.
In the next time period, the next three row electrodes X4 to X6, are selected by applying selection voltages thereto, as shown in FIG. 25B. In accordance with the analysis described above, column voltages have the voltage levels that corresponds to the number of mismatches between the ON and OFF display states of the pixels formed at the intersection of the row electrodes X4 to X6 and the column electrode, and the ON and OFF states of pulse patterns of the synthesized voltages. FIG. 25D illustrates the resultant voltage waveforms that are applied to the pixels at the intersection of the row electrode X1 and column electrode Y1. That is, the synthesized waveform is resultant of the voltage waveform applied to row electrode X1 and the voltage waveform applied to column electrode Y1.
As indicated above, the method that simultaneously selects a plurality of row electrodes in a group and the selection of each group in sequence, has the advantage of the reducing the drive voltage level.
Referring now to FIGS. 27A-27C, the relationship between the transmissitivity of a pixel of a liquid crystal display and the applied voltage is shown therein. In a liquid crystal display driven in a conventional manner, after the selection voltage has been applied to a particular pixel, during the period until the next selection voltage is applied to that pixel, the brightness gradually decreases during the time t. This reduces the transmissitivity T in the ON condition and, on the other hand, slightly increase the transmissitivity T in the OFF condition. As shown in FIG. 21, such conventional displays have poor contrast between the ON condition and the OFF condition.
The following is a general discussion regarding the conventional method for simultaneously selecting multiple row electrodes.
A. Requirements
(1) The N number of row electrodes to be displayed are divided up into N/h non-intersecting subgroups.
(2) Each subgroup has h number of address lines.
(3) At a particular time, the display data on each column electrode is composed of an h-bit words, e.g.:
dk*h+1, dk*h+2 . . . dk*h+h; dk*h+j=0 or 1
Where 0xe2x89xa6kxe2x89xa6(N/h)xe2x88x921 (k: subgroup)
In other words, one column of display data is:
d1, d2 . . . dh . . . Subgroup 0
dh+1, dh+2 . . . dh+h . . . Subgroup 1
dNxe2x88x92h+1, dNxe2x88x92h+2 . . . dNxe2x88x92h+h . . . Subgroup N/hxe2x88x921
(4) The row-select pattern has 2h cycle and is represented by an h-bit words, e.g.:
ak*h+1, ak*h+2 . . . ak*h+h; ak*h+j=0 or 1
B. Guidelines
(1) One subgroup is selected simultaneously for addressing.
(2) One h-bit word is selected as the row-select pattern.
(3) The row-select voltages are:
xe2x88x92Vr for a logic 0,
+Vr for a logic 1,
0 volts or ground for the nonselected period.
(4) The row-select patterns and the display data patterns in the selected subgroup are compared bit by bit such as with digital comparators, viz. exclusive OR logic gates.
(5) The number of mismatches i between these two patterns is determined by counting the number of exclusive-OR logic gates having a logical 1 output.
Steps 1-4 are summarized by the following equation:   i  =            ∑              j        =        1            h        ⁢                  a                              k            *            h                    +          j                    ⊕                        d                                    k              *              h                        +            j                          ⁢                  xe2x80x83                ⁢                  (                      0            ≤            i            ≤            h                    )                    
(where ⊕ is an exclusive OR logic operation)
(6) The column voltage is chosen to be V(i) when the number of mismatches is i.
(7) The column voltages for each column in the matrix is determined independently by repeating the steps (4)-(6).
(8) Both the row voltage and column voltage are applied simultaneously to the matrix display for a time duration xcex94t, where xcex94t is minimum pulse width.
(9) A new row-select pattern is chosen and the column voltages are determined using steps (4)-(6). The new row and column voltages are applied to the display for an equal duration of time at the end of xcex94t.
(10) A frame or cycle is completed when all of the subgroups (=N/h) are selected with all the 2h row-select patterns once.
1 cycle=xcex94txc2x72hxc2x7N/h
C. Analysis
The row select patterns in a case in which there are i number of mismatches will now be considered. The number of h-bit row-select patterns which differ from and h-bit display data pattern by i bits is given by
hCi=h!/{i!(hxe2x88x92i)!}=Ci
For example, when the case for h=3 and row electrode selection pattern=(0,0,0) is considered, the results would be as shown in the table below:
These are determined by the number of bits of a word, not the row electrode selection patterns.
If the amplitude Vpixel of the instantaneous voltage that is applied to the pixel had a row voltage of Vrow and column voltage of Vcolumn, the synthesized voltage would be as follows:
Vpixel=(Vcolumnxe2x88x92Vrow) or (Vrowxe2x88x92Vcolumn)
Where, if Vrow=xc2x1Vr and Vcolumn=V(i), then Vpixel=+Vrxe2x88x92V(i) or xe2x88x92Vrxe2x88x92V(i).
If Vrow=xc2x1Vr and Vcolumn=xc2x1V(i), then Vpixel=Vrxe2x88x92V(i), Vr+V(i), xe2x88x92Vrxe2x88x92V(i) or xe2x88x92Vr+V(i).
That is:
Vpixel=|Vrxe2x88x92V(i)| or |Vr+V(i) |
As a consequence, the specific amplitude to be applied to the pixel is either xe2x88x92(Vr+V(i)) or (Vrxe2x88x92V(i)) in the selection row and is V(i) in the non-selection row.
In general, in order to achieve a high selection ratio, it is desirable that the voltage across a pixel should be as high as possible for an ON pixel and as low as possible for an OFF pixel.
As a result, when a pixel is in the ON state, the voltage |Vr+V(i)| is favorable for the ON pixel, and the voltage |Vrxe2x88x92V(i)| is unfavorable for the ON pixel. On the other hand, when a pixel is in the OFF state, the voltage |Vrxe2x88x92V(i)| is favorable for the OFF pixel, and the voltage |Vr+V(i)| is unfavorable for the OFF pixel.
Here, it is favorable for the ON pixel to increase the effective voltage and unfavorable for the ON pixel to decrease the effective voltage. The number of combinations that selects i units from among the h bits is:
Ci=hCi={h!}/{i!(hxe2x88x92i)!}
The total number of mismatches provides the number of unfavorable voltages in the selected rows in a column. The total number of mismatches is ixc2x7Ci in Ci row select patterns considered are equally distributed over the h pixels in the selected rows. Hence the number of unfavorable voltages per pixel (Bi) when number of mismatches is i can be obtained as given following;
Bi=ixc2x7Ci/h (units/pixel)
The number of times a pixel gets a favorable voltage during the Ci time intervals considered is:
Ai={(hxe2x88x92i)/h}xc2x7Ci
In addition:
{(hxe2x88x92i)/h}xc2x7Ci+(i/h)xc2x7Ci=(h/h) Ci=Ci
Accordingly, the following is obtained:
Ai=Cixe2x88x92Bi={(hxe2x88x921)!}/{i!xc2x7(hxe2x88x92ixe2x88x921)!}
Where: hxe2x89xa6i+1
To summarize the above:
Von(rms)={(S1+S2+S3)/S4}xc2xd
Voff(rms)={(S5+S6+S3)/S4}xc2xd                              S          1                =                              ∑                          i              =              0                        h                    ⁢                                    Ai              ⁡                              (                                                      V                    r                                    +                                      V                                          (                      i                      )                                                                      )                                      2                                              (        favorable        )                                          S          2                =                              ∑                          i              =              0                        h                    ⁢                                    Bi              ⁡                              (                                                      V                    r                                    +                                      V                                          (                      i                      )                                                                      )                                      2                                              (        unfavorable        )                                          S          3                =                              {                                          (                                  N                  /                  h                                )                            -              1                        }                    ⁢                                    ∑                              i                =                0                            h                        ⁢                                          (                                  Ai                  +                  Bi                                )                            ⁢                              V                                  (                  i                  )                                2                                                                        xe2x80x83                                          S          4                =                              2            h                    ·                      (                          N              /              h                        )                                              xe2x80x83                                          S          5                =                              ∑                          i              =              0                        h                    ⁢                                    Ai              ⁡                              (                                                      V                    r                                    -                                      V                                          (                      i                      )                                                                      )                                      2                                              (        favorable        )                                          S          6                =                              ∑                          i              =              0                        h                    ⁢                                    Bi              ⁡                              (                                                      V                    r                                    -                                      V                                          (                      i                      )                                                                      )                                      2                                              (        unfavorable        )            
In addition:
Vr/Vo=Nxc2xd/h . . . row selection voltage
V(i)/V0=(hxe2x88x922i)/h={1xe2x88x92(2i/h)} . . . column voltage, and
R=(Von/Voff)max={(Nxc2xd+1)/(Nxc2xdxe2x88x921)}xc2xd
As noted above and as shown in FIGS. 27A-27C, however, a liquid crystal display driven according to such a method has poor contrast between its ON and OFF states.
Moreover, as shown in FIG. 25, in such conventional driving methods, the pulse width applied to the row electrodes and the column electrodes narrows as the number of simultaneously selected row electrodes increases, and this increases the amount of crosstalk due to the distortion of the waveforms. This results in, for example, poor image quality. This problem becomes even more serious, for example, in a case in which gray shade display, which is caused by the pulse width modulation (PWM), takes place.
Therefore, an object of the present invention is to provide a matrix display apparatus, a matrix display control apparatus, and a matrix display drive apparatus suited to a low power consumption, large capacity display by improving the display data transfer method.
It is an object of the present invention to provide an apparatus that obviates the aforementioned problems of the conventional liquid crystal devices.
It is a further object of the present invention to provide a liquid crystal display for displaying an image having high image quality.
It is another object of the present invention to provide a liquid crystal display with good contrast characteristics.
It is still another object of the present invention to provide a display with a reduced number of column voltage levels.
These and other objects, features and advantages of the present invention will become more apparent upon a consideration of the following detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings.
Although the detailed description and annexed drawings describe a number of preferred embodiments of the present invention, it should be appreciated by those skilled in the art that many variations and modifications of the present invention fall within the spirit and scope of the present invention as defined by the appended claims.
The present invention provides a method combining a module controller-type display device with a signal electrode (X) driver having a built-in frame memory that intermittently operates the oscillation source of a high frequency clock for the module controller during display data transfer.
Specifically, a matrix display apparatus according to the invention comprises a matrix display device of display elements arranged in a matrix pattern, a first random access memory device for storing the display data, a second random access memory device for storing the display data of at least part of the display elements, and a signal electrode drive means for reading the display data from the second memory device to apply a drive voltage to the signal electrodes of the matrix display device. This matrix display apparatus is characterized by an intermittent high frequency oscillator that oscillates according to changes in the display data stored in the first RAM device, and a display data transfer means for reading the display data associated with the change from the first RAM device according to the high frequency clock output from the intermittent high frequency oscillator, and transferring the read display data together with the high frequency clock to the second RAM device.
The matrix display control apparatus for this display apparatus comprises a low frequency oscillator for constantly generating a low frequency clock, a timing signal generator for generating a specified timing signal based on the low frequency clock from the low frequency oscillator, a display data refresh detection means for generating an intermittent control signal based on changes in the display data stored in the first RAM device, an intermittent high frequency oscillator that oscillates according to the intermittent control signal, and a display data transfer means for reading the display data associated with the change from the first RAM device according to the high frequency clock output from the intermittent high frequency oscillator, and transferring the read display data together with the high frequency clock to the second RAM device.
A matrix display drive apparatus comprises a second random access memory device for storing the display data of at least part of the display elements, reads the display data from the second RAM device, and applies a drive voltage to the signal electrodes of the matrix display device. The apparatus used in a display apparatus using this matrix display control apparatus comprises a timing signal generator for generating a write control signal and a read control signal at an offset timing within one scanning period based on the cycle signal received each scanning period, and a read/write means executes a read operation according to the read control signal and then executes a write operation according to the write control signal with both operations addressing the same address in the second RAM device.
A matrix display drive apparatus of this type preferably comprises a clock detection means for detecting when the high frequency clock used for display data transfer stops, and a write prohibit control means for preventing generation of the write control signal based on this detection signal.
The read/write means of this matrix display drive apparatus comprises a temporary storage means for sequentially storing at least one scan line of the incoming display data using the high frequency clock, and a buffer for writing to the second RAM device the stored display data from the temporary storage means according to a signal longer than one cycle of the high frequency clock.
In a matrix display drive apparatus using a multiple line selection drive method, the read/write means comprises a signal voltage state assignment means for extracting the signal voltage to be applied to the signal electrode from the display data read from the second RAM device and the voltage state of the scanning electrode of the matrix display device.
This signal voltage state assignment means specifically comprises a means for reading plural scan lines of display data from the second RAM device on a time-share basis, a temporary storage means that alternately waits for the read display data, a scan state setting means for specifying the voltage state of the scan electrode of the matrix display device, an anti-coincidence detector for detecting anti-coincidence between the plural scan line equivalent display data and the selected voltage state of the scan electrode, and a voltage selector for selecting the signal electrode voltage based on the anti-coincidence detection result.
In a differently configured matrix display drive apparatus using a multiple line selection drive method, the second RAM device comprises a memory array for storing plural scan lines of display data for one line address of the matrix display device, and the signal voltage state assignment means comprises a means for batch reading plural scan lines of display data, a scan state setting means for specifying the voltage state of the scan electrode of the matrix display device, and a voltage selector for selecting the drive voltage from the plural scan line display data read from the second RAM device and the selected voltage state of the scan electrode.
The present invention configured for a uniform distribution, multiple line selection drive method for a scan electrode drive apparatus using a multiple line selection drive method is characterized by a means for simultaneously selecting and cyclically scanning plural scan electrodes plural times within the period of the frame start signal.
A matrix display control apparatus thus comprised can reduce the total power consumption because of intermittent operation of the high frequency clock because the high frequency clock operates only when there is a change in the display data stored in the first RAM device, at which time the display data is transferred to the second RAM device. The processing load on the host MPU for the first RAM device can also be reduced because the transfer process to the second RAM device is executed not by the MPU but by an intermediary matrix display control apparatus. By cascade connecting the drive device of the signal electrodes, display data can be transferred according to the configuration of the matrix display device without being aware of the driver side memory configuration, and the address correlation process can be simplified. The display can also be refreshed faster because the display data for each scan line is stored in the second RAM device. By cascade connecting the signal electrode drive devices, the number of connections (e.g., the number of chip selection buses) between the matrix display control apparatus and drive devices can be minimized even in large capacity displays, and display devices with a large display area ratio can be achieved.
In addition, the second RAM device can be accessed with ease using time-share access timing during one scanning period. Greater tolerance is therefore achieved in the second RAM device access timing, improving data writing performance and making it possible to reduce the size of the transistors in the second RAM device. This also contributes to a reduction in driver chip size.
According to an additional aspect of the present invention, a multiplex driving method is provided for a liquid crystal display device having a liquid crystal layer disposed between a pair of substrates, a plurality of row electrodes arranged on one of the substrates and a plurality of column electrodes arranged on the other substrate. The method comprises the steps of sequentially selecting a group of the plurality of row electrodes in a selection period, simultaneously selecting the row electrodes comprising each group, and dividing and separating the selection period into a plurality of intervals within one frame period.
By adopting such a driving method, for example, after a selection voltage has been applied to a particular pixel in the initial frame, the voltage will be applied to that pixel several times during the period until the selection voltage is applied to that pixel in the next frame. This makes it possible to maintain brightness and prevent a reduction in contrast.
According to another aspect of the present invention, a first portion of a selection signal is sequentially applied to each of j groups of row electrodes in a first selection period of a frame, such that the first portion of the selection signal is simultaneously applied to i row electrodes in each of the j groups. A second portion of the selection signal is sequentially applied to the j groups of row electrodes in a second selection period of the frame, such that the second portion of the selection signal is simultaneously applied to the i row electrodes in each of the j groups.
According to a further aspect of the present invention, a display apparatus is provided comprising a display having a plurality of row electrodes and column electrodes, the row electrodes being arranged in groups. A drive circuit comprises a row electrode data generating circuit for generating row selection pulse data and a frame memory for providing display data. An arithmetic operation circuit calculates converted data in accordance with the row selection pulse data generated by the drive circuit and the display data provided by the frame memory. A column electrode driver is responsive to the converted data calculated by the arithmetic operation circuit for generating column data for the plurality of column electrodes. A row electrode driver is responsive to the row selection pulse data generated by said drive circuit for selecting in sequence each of the groups of row electrodes. The row electrodes comprising each of the groups are selected simultaneously, and scanning of one screen is performed a plurality of times in accordance with the row selection pulse data and the display data during one frame period. By having a drive circuit such as that described above, it is possible to execute the drive method described above easily and reliably.
In accordance with such a display device, the display device has a driving circuit which performs the steps of calculating the row-select pattern generated by the row electrode data generation circuit and the display data pattern on the plurality of row electrodes which are read in sequence from the frame memory. The row electrodes are then selected simultaneously with the row-select pattern. The driving circuit transfers the converted data, which is the result of the calculation, to the column electrode driver, and transfers the row data, which is generated by the row electrode data generation circuit, to the row electrode driver. Further, the driving circuit repeats the above-mentioned operation by the next row-select pattern data and display data pattern when scanning of one image is finished. The screen operation is repeated several times in one frame period. Thus, the display device according to the present invention has excellent contrast characteristics.
According to still yet a further aspect of the present invention, a method is provided for determining a number of voltage levels applied to each of m column electrodes in a liquid crystal display having a pair of opposing substrates, n row electrodes disposed on one of the substrates and the m column electrodes disposed on the other of the substrates, and a liquid crystal material disposed between the pair of substrates, n x m pixels being formed at the intersection of the n row electrodes and the m column electrodes. The n row electrodes are divided into j groups, each group having at least i row electrodes, i, j, n and m being positive integers greater than 1, i being less than n and j being less than n. A selection signal is applied sequentially to each of the j groups of row electrodes and simultaneously applied to each of the i row electrodes in a plurality of time periods for displaying an image in a frame period. The method comprising the step of, for each of the time periods, determining a first number of mismatches between the selection signal applied to the i row electrodes and display states of the pixels formed at the intersections of the i row electrodes and one of the m columns electrodes. A virtual selection signal is applied to a virtual row electrode and a second number of mismatches between the virtual selection signal applied to the virtual electrode and a display state of a virtual pixel formed at the intersection of the one column electrode and the virtual row electrode is determined. A third number of mismatches is defined by the sum of the first and second number of mismatches, and the virtual selection signal has a waveform and the virtual pixel has a display state such that the third number of mismatches is either an odd number or an even number. A number of matches between the selection signal applied to the i row electrodes and the display states of the pixels at the intersections of the i row electrodes and the one column electrode and between the virtual selection signal applied to the virtual row electrode and the display state of the virtual pixel formed at the intersection of the virtual electrode and the one column electrode is determined. The voltage level for each time period is a level corresponding to the difference between the third number of mismatches and the number of matches. The above-discussed process is repeated for each of the time periods.